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TJA1081
FlexRay node transceiver
Rev. 01 -- 15 April 2009
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Preliminary data sheet
1. General description
The TJA1081 is a FlexRay node transceiver that is fully compliant with the FlexRay electrical physical layer specification V2.1 Rev. A (see Ref. 1) and partly complies with versions V2.1 Rev. B. In addition, the TJA1081 already incorporates features and parameters anticipated to be included in V3.0, currently being finalized. It is primarily intended for communication systems from 1 Mbit/s to 10 Mbit/s, and provides an advanced interface between the protocol controller and the physical bus in a FlexRay network. The TJA1081 features enhanced low-power modes, optimized for ECUs that are permanently connected to the battery. The TJA1081 provides differential transmit capability to the network and differential receive capability to the FlexRay controller. It offers excellent EMC performance as well as high ESD protection. The TJA1081 actively monitors system performance using dedicated error and status information (that can be read by any microcontroller), along with internal voltage and temperature monitoring. The TJA1081 supports mode control as used in the TJA1080A (see Ref. 2).
2. Features
2.1 Optimized for time triggered communication systems
I I I I I I I I I I Compliant with FlexRay electrical physical layer specification V2.1 Rev. A (see Ref. 1) Automotive product qualification in accordance with AEC-Q100 Data transfer up to 10 Mbit/s Support of 60 ns minimum bit time Very low ElectroMagnetic Emission (EME) to support unshielded cable Differential receiver with wide common-mode range for high ElectroMagnetic Immunity (EMI) Auto I/O level adaptation to host controller supply voltage VIO Can be used in 14 V and 42 V powered systems Bus guardian interface Independent power supply ramp-up for VBAT, VCC and VIO
2.2 Low power management
I Low power management including inhibit switch I Very low current in Sleep and Standby modes
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I Local and remote wake-up I Supports remote wake-up via dedicated data frames I Wake-up source recognition
2.3 Diagnosis (detection and signalling)
I I I I I I Overtemperature detection Short-circuit on bus lines VBAT power-on flag (first battery connection and cold start) Pin TXEN and pin BGE clamping Undervoltage detection on pins VBAT, VCC and VIO Wake source indication
2.4 Protections
I Bus pins protected against 8 kV HBM ESD pulses I Bus pins protected against transients in automotive environment (ISO 7637 class C compliant) I Bus pins short-circuit proof to battery voltage (14 V and 42 V) and ground I Fail-silent behavior in the event of an undervoltage on pins VBAT, VCC or VIO I Passive behavior of bus lines while the transceiver is not powered
2.5 Functional classes according to FlexRay electrical physical layer specification (see Ref. 1)
I Bus driver voltage regulator control I Bus driver - bus guardian control interface I Bus driver logic level adaptation
3. Ordering information
Table 1. Ordering information Package Name TJA1081TS SSOP16 Description SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm Version SOT338-1 Type number
TJA1081_1
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Preliminary data sheet
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4. Block diagram
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VIO 3 VCC 16 VBAT 11 1
INH
TJA1081
15 SIGNAL ROUTER TRANSMITTER 14
BP BM
VIO
TXD TXEN BGE STBN EN
4 5 7 8 2 INPUT VOLTAGE ADAPTATION BUS FAILURE DETECTION
RXD ERRN RXEN
6 10 9 VBAT
OUTPUT VOLTAGE ADAPTATION
RXDINT STATE MACHINE RXDINT NORMAL RECEIVER
WAKE
12
WAKE-UP DETECTION
OVERTEMPERATURE DETECTION
OSCILLATOR LOWPOWER RECEIVER
UNDERVOLTAGE DETECTION
13
015aaa066
GND
Fig 1.
Block diagram
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5. Pinning information
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5.1 Pinning
INH EN VIO TXD TXEN RXD BGE STBN
1 2 3 4 5 6 7 8
015aaa067
16 VCC 15 BP 14 BM 13 GND 12 WAKE 11 VBAT 10 ERRN 9 RXEN
TJA1081
Fig 2.
Pin configuration
5.2 Pin description
Table 2. Symbol INH EN VIO TXD TXEN RXD BGE STBN RXEN ERRN VBAT WAKE GND BM BP VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type O I P I I O I I O O P I P I/O I/O P Description inhibit output for switching external voltage regulator enable input; enabled when HIGH; internal pull-down supply voltage for VIO voltage level adaptation transmit data input; internal pull-down transmitter enable input; when HIGH transmitter disabled; internal pull-up receive data output bus guardian enable input; when LOW transmitter disabled; internal pull-down standby input; low-power mode when LOW; internal pull-down receive data enable output; when LOW bus activity detected error diagnoses output; when LOW error detected battery supply voltage local wake-up input; internal pull-up or pull-down (depends on voltage at pin WAKE) ground bus line minus bus line plus supply voltage (+5 V)
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6. Functional description
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The block diagram of the transceiver is shown in Figure 1.
6.1 Operating modes
The TJA1081 supports the following operating modes:
* * * * *
Normal (normal-power mode) Receive-only (normal-power mode) Standby (low-power mode) Go-to-sleep (low-power mode) Sleep (low-power mode)
6.1.1 Bus activity and idle detection
The following mechanisms for activity and idle detection are valid in normal-power modes:
* If the absolute differential voltage on the bus lines is higher than |Vi(dif)det(act)| for
tdet(act)(bus), activity is detected on the bus lines and pin RXEN is switched LOW which results in pin RXD being released: - If, after bus activity detection, the differential voltage on the bus lines is higher than VIH(dif), pin RXD will go HIGH - If, after bus activity detection, the differential voltage on the bus lines is lower than VIL(dif), pin RXD will go LOW
* If the absolute differential voltage on the bus lines is lower than |Vi(dif)det(act)| for
tdet(idle)(bus), then idle is detected on the bus lines and pin RXEN is switched to HIGH. This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH)
6.2 Mode control pins: STBN and EN
Control inputs STBN and EN are used to select the operating mode. See Table 3 for a detailed description of pin signalling and Figure 3 for the timing diagram. All mode transitions are controlled via the STBN and EN pins, unless an undervoltage condition is detected. If VIO and (VCC or VBAT) are within their specified operating ranges, pin ERRN will indicate the status of the error flag.
Table 3. Mode Normal Receive-only Go-to-sleep Standby Sleep
[1] [2]
Pin signalling STBN EN ERRN[1] LOW HIGH LOW LOW LOW LOW HIGH HIGH error flag set HIGH error flag [2] LOW set X HIGH error flag reset error flag reset RXEN LOW bus activity bus idle RXD HIGH LOW bus DATA_0 wake flag set[2] HIGH bus DATA_1 or idle wake flag reset float enabled disabled HIGH Transmitter INH
wake flag wake set[2] flag reset
Pin ERRN provides a serial interface for retrieving diagnostic information. Valid if VIO and (VCC or VBAT) are present.
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TXD www..com
BGE
TXEN
BP BM
RXEN
RXD
001aae439
Fig 3.
Timing diagram in Normal mode
normal
receive only
standby
receive only
normal
STBN tdet(EN)
0.7VIO 0.3VIO td(STBN-stb) td(STBN-RXD) 0.7VIO 0.3VIO tdet(EN)
EN
ERRN
S2
015aaa068
Fig 4.
Timing diagram of control pins EN and STBN
The state diagram is shown in Figure 5.
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1 RECEIVE ONLY STBN = HIGH EN = LOW 4 NORMAL STBN = HIGH EN = HIGH
3, 30 15, 25, 42, 43 31, 32 8, 17, 39 6, 33 11, 21
5 10, 20 7, 16, 38 2 14, 24, 40, 41 28, 29
12, 22 STANDBY(1) 19 STBN = LOW EN = LOW 9, 18 GO-TO-SLEEP STBN = LOW EN = HIGH 23
36, 37 26, 44
13, 34, 35 27, 45
SLEEP STBN = LOW EN = X
001aae438
(1) At the first battery connection the transceiver will enter the Standby mode.
Fig 5.
State diagram
The state transitions are represented with numbers, which correspond with the numbers in column 3 of Table 4 to Table 7.
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Table 4. State transitions forced by EN and STBN indicates the action that initiates a transaction; 1 and 2 indicated the consequences of a transaction. Transition from mode Normal Direction to mode Transition number Pin STBN H L L H L L H H L H H L L H H EN L H L H H L H L H H L L H H L Flag UVVIO cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared 2 cleared 2 cleared UVVBAT cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared 2 cleared 2 cleared UVVCC cleared cleared cleared cleared cleared cleared 2 cleared 2 cleared X cleared cleared X X 2 cleared 2 cleared PWON cleared cleared cleared X X X X X X X X X X X X Wake cleared cleared cleared X X X 1 cleared 1 set X 1 cleared 1 set X cleared 1 cleared 1 set
Note
Receive-only 1 Go-to-sleep Standby 2 3 4 5 6 7 9 10 12 13 14
[1]
Receive-only Normal Go-to-sleep Standby Standby Normal Go-to-sleep Go-to-sleep Normal Standby Sleep Sleep Normal
[2][3] [2][3]
Receive-only 8
[2][4] [2][4] [4] [5] [2][3] [2][3]
Receive-only 11
Receive-only 15
[1] [2] [3] [4] [5]
STBN must be set to LOW at least tdet(EN) after the falling edge on EN. Positive edge on pin STBN sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared. Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flags. Hold time of go-to-sleep is less than th(gotosleep). Hold time of go-to-sleep becomes greater than th(gotosleep).
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Table 5. State transitions forced by a wake-up indicates the action that initiates a transaction; 1 and 2 indicated the consequences of a transaction. Transition from mode Standby Direction to mode Normal Receive-only Go-to-sleep Standby Go-to-sleep Normal Receive-only Standby Go-to-sleep Sleep Normal Receive-only Standby Go-to-sleep
[1] [2]
Transition number 16 17 18 19 20 21 22 23 24 25 26 27
Pin STBN H H L L H H L L H H L L EN H L H L H L L H H L L H
Flag UVVIO cleared cleared cleared cleared cleared cleared cleared cleared 1 cleared 1 cleared 1 cleared 1 cleared UVVBAT cleared cleared cleared cleared cleared cleared cleared cleared 1 cleared 1 cleared 1 cleared 1 cleared UVVCC 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared PWON X X X X X X X X X X X X Wake set set set set set set set set set set set set
Note
[1] [1] [1] [1] [1] [1] [1] [1] [1][2] [1][2] [1] [1][2]
Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flags. Transition via Standby mode.
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Table 6. State transitions forced by an undervoltage condition indicates the action that initiates a transaction; 1 and 2 indicated the consequences of a transaction. Transition from mode Normal Direction to mode Sleep Sleep Standby Receive-only Sleep Sleep Standby Go-to-sleep Standby Sleep Sleep Sleep Sleep
[1] [2] [3]
Transition number 28 29 30 31 32 33 34 35 36 37
Flag UVVIO set cleared cleared set cleared cleared set cleared set cleared UVVBAT cleared set cleared cleared set cleared cleared set cleared set UVVCC cleared cleared set cleared cleared set cleared cleared X X PWON cleared cleared cleared X X X X X X X Wake cleared cleared cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared 1 cleared
Note
[1] [1] [1] [1] [1] [1] [1] [1] [1][2] [1][3]
UVVIO, UVVBAT or UVVCC detected clears the wake flag. UVVIO overrules UVVCC. UVVBAT overrules UVVCC.
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Table 7. State transitions forced by an undervoltage recovery indicates the action that initiates a transaction; 1 and 2 are the consequences of a transaction. Transition from mode Standby Sleep Direction to mode Normal Normal Normal Transition number 38 40 41 Pin STBN H H H H H H L L L L EN H L H H L L L X H X Flag UVVIO cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared UVVBAT cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared UVVCC cleared cleared cleared cleared cleared cleared cleared cleared cleared cleared PWON X X X X X X X X X X Wake X X 1 cleared X 1 set X 1 set cleared 1 set cleared
Note
[1] [1] [2][3] [4] [2][3] [4] [2][3] [4] [2][3] [4]
Receive-only 39
Receive-only 42 Receive-only 43 Standby Sleep Go-to-sleep Sleep
[1] [2] [3] [4] Recovery of UVVCC flag. Recovery of UVVBAT flag.
44 45 46 47
Clearing the UVVBAT flag sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared. Recovery of UVVIO flag.
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6.2.1 Normal mode
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In Normal mode the transceiver is able to transmit and receive data via the bus lines BP and BM. The output of the normal receiver is directly connected to pin RXD. Transmitter behavior in Normal mode, with no time-out present on pins TXEN and BGE and the temperature flag not set (TEMP HIGH = 0; see Table 9), is detailed in Table 8. In this mode, pin INH is set HIGH.
Table 8. BGE L X H H X H L L Transmitter function table TXEN TXD X X H L Transmitter transmitter is disabled transmitter is disabled transmitter is enabled; the bus lines are actively driven; BP is driven HIGH and BM is driven LOW transmitter is enabled; the bus lines are actively driven; BP is driven LOW and BM is driven HIGH
6.2.2 Receive-only mode
In Receive-only mode the transceiver can only receive data. The transmitter is disabled, regardless of the voltage levels on pins BGE and TXEN. In this mode, pin INH is set HIGH.
6.2.3 Standby mode
Standby mode is a low-power mode featuring very low current consumption. In this mode, the transceiver cannot transmit or receive data. The low-power receiver is activated to monitor the bus for wake-up patterns. A transition to Standby mode can be triggered by applying the appropriate levels on pins EN and STBN (see Figure 5 and Table 4) or if an undervoltage is detected on pin VCC (see Figure 5 and Section 6.2.5). In this mode, pin INH is set HIGH. If the wake flag is set, pins RXEN and RXD are driven LOW; otherwise pins RXEN and RXD are set HIGH (see Section 6.3).
6.2.4 Go-to-sleep mode
In this mode, the transceiver behaves as in Standby mode. If this mode is selected for a time longer than the go-to-sleep hold time (th(gotosleep)) and the wake flag has been previously cleared, the transceiver will enter Sleep mode, regardless of the voltage on pin EN.
6.2.5 Sleep mode
Sleep mode is a low-power mode. The only difference between Sleep mode and Standby mode is that pin INH is set floating in Sleep mode. A transition to Sleep mode will be triggered from all other modes if the UVVIO flag or the UVVBAT flag is set (see Table 6). If an undervoltage is detected on pin VCC or VBAT while VIO is present, the wake flag is set by a positive edge on pin STBN, provided that VIO and (VCC or VBAT) are present.
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The undervoltage flags will be reset when the wake flag is set, and the transceiver will enter the mode indicated by the levels on pins EN and STBN if VIO is present.
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6.3 Wake-up mechanism
From Sleep mode (pin INH is switched off), the transceiver will enter Standby or Go-to-sleep mode (depending on the level at pin EN) if the wake flag is set. Consequently, pin INH is switched on. If an undervoltage is not detected on pins VIO, VCC and VBAT, the transceiver will switch immediately to the mode indicated by the levels on pins EN and STBN. In Standby, Go-to-sleep and Sleep modes, pins RXD and RXEN are driven LOW if the wake flag is set.
6.3.1 Remote wake-up
6.3.1.1 Bus wake-up via wake-up pattern Bus wake-up is detected if two consecutive DATA_0 of at least tdet(wake)DATA_0 separated by an idle or DATA_1 of at least tdet(wake)idle, followed by an idle or DATA_1 of at least tdet(wake)idle are present on the bus lines within tdet(wake)tot.
tdet(wake)tot
0V Vdif -425 mV tdet(wake)Data_0 tdet(wake)idle tdet(wake)Data_0 tdet(wake)idle
001aae442
Fig 6.
Bus wake-up timing
6.3.1.2
Bus wake-up via dedicated FlexRay data frame The reception of a dedicated data frame, emulating a valid wake-up pattern, as shown in Figure 7, sets the wake-up flag of the TJA1081. Due to the Byte Start Sequence (BSS), preceding each byte, the DATA_0 and DATA_1 phases for the wake-up symbol are interrupted every 1 s. For 10 Mbit/s the maximum interruption time is 130 ns. Such interruptions do not prevent the transceiver from recognizing the wake-up pattern in the payload of a data frame. The wake-up flag will not be set if an invalid wake-up pattern is received.
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+1500 0V -1500
Vdif 130 ns 870 ns 870 ns wake-up
770 870 870 ns ns ns 5 s
130 130 ns ns 5 s 5 s 5 s
015aaa043
Each interruption is 130 ns. The transition time from Data_0 to Data_1 and from Data_1 to Data_0 is about 20 ns. The TJA1081 wake-up flag will be set with the following pattern: FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, FFh
Fig 7.
Minimum bus pattern for bus wake-up
6.3.2 Local wake-up via pin WAKE
If the voltage on pin WAKE is lower than Vth(det)(WAKE) for longer than twake(WAKE) (falling edge on pin WAKE) a local wake-up event on pin WAKE is detected. At the same time, the biasing of this pin is switched to pull-down. If the voltage on pin WAKE is higher than Vth(det)(WAKE) for longer than twake(WAKE), the biasing of this pin is switched to pull-up, and no local wake-up will be detected.
pull-up twake(WAKE) VBAT WAKE 0V
pull-down twake(WAKE)
pull-up
RXD and RXEN
VBAT INH 0V
015aaa069
Sleep mode: VIO and (VBAT or VCC) still provided.
Fig 8.
Local wake-up timing via pin WAKE
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6.4 Fail-silent behavior
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In order to be fail silent, undervoltage detection and a reset mechanism for the digital state machine are implemented. If an undervoltage is detected on pins VCC, VIO and/or VBAT, the transceiver will enter a low-power mode. This ensures the passive and defined behavior of the transmitter and receiver when an undervoltage is detected. In the range between the minimum operating voltage and the undervoltage detection threshold, the principle functions of the transmitter and receiver are maintained. However, in this range parameters (e.g. thresholds and delays of the transmitter and receiver) may deviate from the levels specified for the operating range. The digital state machine is supplied by VCC, VIO or VBAT, depending on which voltage is available. Therefore, the digital state machine will be properly supplied as long as the voltage on pin VCC or pin VIO remains above 4.75 V or the voltage on pin VBAT remains above 6.5 V. If the voltage on all pins (i.e. VCC, VIO and VBAT) breaks down, a reset signal will be given to the digital state machine as soon as the internal supply voltage for the digital state machine becomes too low for the proper operation of the state machine. This ensures the passive and defined behavior of the digital state machine in the event of an overall supply voltage breakdown.
6.4.1 VBAT undervoltage
If the UVVBAT flag is set, the transceiver will enter Sleep mode (pin INH is switched off) regardless of the voltages present on pins EN and STBN. If the undervoltage recovers, the wake flag will be set and the transceiver will enter the mode determined by the voltages on pins EN and STBN.
6.4.2 VCC undervoltage
If the UVVCC flag is set, the transceiver will enter Standby mode regardless of the voltages present on pins EN and STBN. If the undervoltage recovers or the wake flag is set, mode switching via pins EN and STBN is possible.
6.4.3 VIO undervoltage
If the voltage on pin VIO is lower than Vuvd(VIO) (even if the UVVIO flag is reset) pins EN, STBN, TXD and BGE are set LOW (internally) and pin TXEN is set HIGH (internally). If the UVVIO flag is set, the transceiver will enter Sleep mode (pin INH is switched off). If the undervoltage recovers or the wake flag is set, mode switching via pins EN and STBN is possible.
6.5 Flags
6.5.1 Local wake-up source flag
The local wake-up source flag can only be set in a low-power mode. When a wake-up event is detected on pin WAKE (see Section 6.3.2), the local wake-up source flag is set. The local wake-up source flag is reset by entering a low-power mode.
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6.5.2 Remote wake-up source flag
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The remote wake-up source flag can only be set in a low-power mode if pin VBAT is within its operating range. When a remote wake-up event is detected on the bus lines (see Section 6.3.1), the remote wake-up source flag is set. The remote wake-up source flag is reset by entering a low-power mode.
6.5.3 Wake flag
The wake flag is set if one of the following events occurs:
* The local or remote wake-up source flag is set (edge sensitive) * A positive edge is detected on pin STBN when VIO is present * Recovery of the UVVBAT flag
The wake flag is reset by entering Normal mode, a low-power mode or by setting one of the undervoltage flags.
6.5.4 Power-on flag
The PWON flag is set if the internal supply voltage for the digital part becomes higher than the lowest value it needs to operate. Entering Normal mode resets the PWON flag.
6.5.5 Temperature medium flag
The temperature medium flag is set if the junction temperature exceeds Tj(warn)(medium) in a normal-power mode while pin VBAT is within its operating range. The temperature medium flag is reset when the junction temperature drops below Tj(warn)(medium) in a normal-power mode with pin VBAT within its operating range or after a read of the status register in a low-power mode while pin VBAT is within its operating range. No action will be taken if this flag is set.
6.5.6 Temperature high flag
The temperature high flag is set if the junction temperature exceeds Tj(dis)(high) in a normal-power mode while pin VBAT is within its operating range. The temperature high flag is reset if a negative edge is applied to pin TXEN while the junction temperature is lower than Tj(dis)(high) in a normal-power mode with pin VBAT within its operating range. If the temperature high flag is set, the transmitter will be disabled.
6.5.7 TXEN_BGE clamped flag
The TXEN_BGE clamped flag is set if pin TXEN is LOW and pin BGE is HIGH for longer than tdetCL(TXEN_BGE). The TXEN_BGE clamped flag is reset if pin TXEN is HIGH or pin BGE is LOW. If the TXEN_BGE flag is set, the transmitter is disabled.
6.5.8 Bus error flag
The bus error flag is set if pin TXEN is LOW and pin BGE is HIGH and the data received from the bus lines (pins BP and BM) are different to that received on pin TXD. The transmission of any valid communication element, including a wake-up pattern, does not lead to bus error indication.
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The error flag is reset if the data on the bus lines (pins BP and BM) are the same as on pin TXD or if the transmitter is disabled. No action will be taken if the bus error flag is set.
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6.5.9 UVVBAT flag
The UVVBAT flag is set if the voltage on pin VBAT is lower than Vuvd(VBAT). The UVVBAT flag is reset if the voltage is higher than Vuvd(VBAT) or by setting the wake flag; see Section 6.4.1.
6.5.10 UVVCC flag
The UVVCC flag is set if the voltage on pin VCC is lower than Vuvd(VCC) for longer than tdet(uv)(VCC). The flag is reset if the voltage on pin VCC is higher than Vuvd(VCC) for longer than trec(uv)(VCC) or the wake flag is set; see Section 6.4.2.
6.5.11 UVVIO flag
The UVVIO flag is set if the voltage on pin VIO is lower than Vuvd(VIO) for longer than tdet(uv)(VIO). The flag is reset if the voltage on pin VIO is higher than Vuvd(VIO) or the wake flag is set; see Section 6.4.3.
6.5.12 Error flag
The error flag is set if one of the status bits S4 to S10 is set. The error flag is reset if none of the S4 to S10 status bits are set; see Table 9.
6.6 Status register
The status register can be read out on pin ERRN by using pin EN as clock; the status bits are given in Table 9. The timing diagram is shown in Figure 9. The status register is accessible if:
* UVVIO flag is not set and the voltage on pin VIO is between 4.75 V and 5.25 V * UVVCC flag is not set and the voltage on pin VIO is between 2.2 V and 4.75 V
After reading the status register, if no edge is detected on pin EN for longer than tdet(EN), the status bits (S4 to S12) will be cleared if the corresponding flag has been reset. Pin ERRN is LOW if the corresponding status bit is set.
Table 9. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 Status bits Description local wake-up source flag is redirected to this bit remote wake-up source flag is redirected to this bit not used; always set status bit set means PWON flag has been set previously status bit set means bus error flag has been set previously status bit set means temperature high flag has been set previously status bit set means temperature medium flag has been set previously status bit set means TXEN_BGE clamped flag has been set previously status bit set means UVVBAT flag has been set previously status bit set means UVVCC flag has been set previously LOCAL WAKEUP REMOTE WAKEUP PWON BUS ERROR TEMP HIGH TEMP MEDIUM TXEN_BGE CLAMPED UVVBAT UVVCC
Bit number Status bit
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Table 9. S10
Status bits ...continued Description status bit set means UVVIO flag has been set previously not used; always reset not used; always reset UVVIO
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Bit number Status bit -
S11 S12
normal
receive only
STBN tdet(EN) 0.7VIO
0.7VIO
EN TEN 0.7VIO 0.3VIO
td(EN-ERRN) S0 S1 S2
001aag896
ERRN
Fig 9.
Timing diagram for status bits
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7. Limiting values
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Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol VBAT VCC VIO VINH IO(INH) VWAKE Io(WAKE) VBGE VTXEN VTXD VERRN VRXD VRXEN VEN VSTBN VBP VBM Vtrt Parameter supply voltage on pin VBAT supply voltage supply voltage on pin VIO voltage on pin INH output current on pin INH voltage on pin WAKE output current on pin WAKE voltage on pin BGE voltage on pin TXEN voltage on pin TXD voltage on pin ERRN voltage on pin RXD voltage on pin RXEN voltage on pin EN voltage on pin STBN voltage on pin BP voltage on pin BM transient voltage pin GND not connected no time limit no time limit no time limit no time limit no time limit no time limit no time limit no time limit no time limit no time limit on pins BP and BM on pin VBAT on pin VBAT on pin VBAT Tstg Tvj VESD storage temperature virtual junction temperature electrostatic discharge voltage HBM on pins BP and BM to ground HBM at any other pin MM on all pins CDM on all pins
[1] [2] [3] [4] [5] [6] [7] [8]
[5] [6] [6] [7] [8] [1] [2] [3] [4]
Conditions no time limit operating range no time limit operating range no time limit operating range no time limit
Min -0.3 6.5 -0.3 4.75 -0.3 2.2 -0.3 -1 -0.3 -15 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -60 -60 -200 -200 6.5 -55 -40 -8.0 -4.0 -200 -1000
Max +60 60 +5.5 5.25 +5.5 5.25 VBAT + 0.3 VBAT + 0.3 +5.5 +5.5 +5.5 VIO + 0.3 VIO + 0.3 VIO + 0.3 +5.5 +5.5 +60 +60 +200 +200 60 60 +150 +150 +8.0 +4.0 +200 +1000
Unit V V V V V V V mA V mA V V V V V V V V V V V V V V C C kV kV V V
According to ISO 7637, part 3 test pulses a and b; Class C; see Figure 13; Rbus = 45 ; Cbus = 100 pF. According to ISO 7637, part 2 test pulses 1, 2, 3a and 3b; Class C; see Figure 13; Rbus = 45 ; Cbus = 100 pF. According to ISO 7637, part 2 test pulse 4; Class C; see Figure 13; Rbus = 45 ; Cbus = 100 pF. According to ISO 7637, part 2 test pulse 5b; Class C; see Figure 13; Rbus = 45 ; Cbus = 100 pF; VBAT = 24 V. In accordance with IEC 60747-1. An alternative definition of Tvj is: Tvj = Tamb + P x Rth(j-a), where Rth(j-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). HBM: C = 100 pF; R = 1.5 k. MM: C = 200 pF; L = 0.75 H; R = 10 . CDM: R = 1 .
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8. Thermal characteristics
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Table 11. Symbol Rth(j-a)
Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 118 Unit K/W
9. Static characteristics
Table 12. Static characteristics All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Pin VBAT IBAT supply current on pin VBAT low-power modes; no load on pin INH normal-power modes Vuvd(VBAT) Pin VCC ICC supply current low-power modes Normal mode; VBGE = 0 V; VTXEN = VIO; Receive-only mode Normal mode; VBGE = VIO; VTXEN = 0 V Normal mode; VBGE = VIO; VTXEN = 0 V; Rbus = Vuvd(VCC) Pin VIO IIO supply current on pin VIO low-power modes Normal and Receive-only modes; VTXD = VIO Vuvd(VIO) Vuvr(VIO) Vuvhys(VIO) Pin EN VIH(EN) VIL(EN) IIH(EN) IIL(EN) Pin STBN VIH(STBN) VIL(STBN) IIH(STBN) IIL(STBN)
TJA1081_1
Parameter
Conditions
Min 2.75
Typ -
Max 55 1 4.5
Unit A mA V
undervoltage detection voltage on pin VBAT
-1 -
0 -
+10 15
A mA
-
-
37 15
mA mA
undervoltage detection voltage on pin VCC VBAT > 5.5 V
2.75 -1 1 1 25 0.7VIO -0.3
+1 0 0
4.5 +10 1000 2 2.2 200 5.5 0.3VIO 11 +1 5.5 0.3VIO 11 +1
V A A V V mV V V A A V V A A
20 of 36
undervoltage detection voltage on pin VIO undervoltage recovery voltage on pin VIO undervoltage hysteresis voltage on pin VIO VBAT > 5.5 V HIGH-level input voltage on pin EN LOW-level input voltage on pin EN HIGH-level input current on pin EN LOW-level input current on pin EN HIGH-level input voltage on pin STBN LOW-level input voltage on pin STBN HIGH-level input current on pin STBN LOW-level input current on pin STBN VSTBN = 0.7VIO VSTBN = 0 V VEN = 0.7VIO VEN = 0 V
3 -1 0.7VIO -0.3 3 -1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 April 2009
NXP Semiconductors
TJA1081
FlexRay node transceiver
Table 12. Static characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. www..com Symbol Pin TXEN VIH(TXEN) VIL(TXEN) IIH(TXEN) IIL(TXEN) IL(TXEN) Pin BGE VIH(BGE) VIL(BGE) IIH(BGE) IIL(BGE) Pin TXD VIH(TXD) VIL(TXD) IIH(TXD) IIL(TXD) HIGH-level input voltage on pin TXD LOW-level input voltage on pin TXD HIGH-level input current on pin TXD LOW-level input current on pin TXD normal-power modes normal-power modes VTXD = VIO normal-power modes; VTXD = 0 V low-power modes ILI(TXD) Ci(TXD) input leakage current on pin TXD input capacitance on pin TXD VTXD = 5.25 V; VIO = 0 V not tested; with respect to all other pins at ground; VTXD = 100 mV; f = 5 MHz VRXD = VIO - 0.4 V; VIO = VCC VRXD = 0.4 V VERRN = VIO - 0.4 V; VIO = VCC VERRN = 0.4 V VRXEN = VIO - 0.4 V; VIO = VCC VRXEN = 0.4 V Normal or Receive-only mode; VTXEN = VIO Standby, Go-to-sleep or Sleep mode
[1]
Parameter HIGH-level input voltage on pin TXEN LOW-level input voltage on pin TXEN HIGH-level input current on pin TXEN LOW-level input current on pin TXEN leakage current on pin TXEN HIGH-level input voltage on pin BGE LOW-level input voltage on pin BGE HIGH-level input current on pin BGE LOW-level input current on pin BGE
Conditions
Min 0.7VIO -0.3
Typ 0 0 0 300 0 0 0 5
Max 5.5 0.3VIO +1 -3 +1 5.5 0.3VIO 11 +1 VIO + 0.3 0.3VIO 650 +5 +1 +1 10
Unit V V A A A V V A A V V A A A A pF
VTXEN = VIO VTXEN = 0.3VIO VTXEN = 5.25 V; VIO = 0 V
-1 -15 -1 0.7VIO -0.3
VBGE = 0.7VIO VBGE = 0 V
3 -1 0.7VIO -0.3 70 -5 -1 -1 -
Pin RXD IOH(RXD) IOL(RXD) Pin ERRN IOH(ERRN) IOL(ERRN) Pin RXEN IOH(RXEN) IOL(RXEN) Vo(idle)(BP) HIGH-level output current on pin RXEN LOW-level output current on pin RXEN idle output voltage on pin BP -4 1 -1.5 3 -0.5 8 mA mA HIGH-level output current on pin ERRN LOW-level output current on pin ERRN -1500 300 -550 700 -100 1500 A A HIGH-level output current on pin RXD LOW-level output current on pin RXD -20 2 -2 20 mA mA
Pins BP and BM 0.4VCC 0.5VCC 0.6VCC V -0.1 0 +0.1 V
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Table 12. Static characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. www..com Symbol Vo(idle)(BM) Parameter idle output voltage on pin BM Conditions Normal or Receive-only mode; VTXEN = VIO Standby, Go-to-sleep or Sleep mode Io(idle)BP Io(idle)BM Vo(idle)(dif) VOH(dif) VOL(dif) VIH(dif) idle output current on pin BP idle output current on pin BM differential idle output voltage differential HIGH-level output voltage differential LOW-level output voltage differential HIGH-level input voltage 40 Rbus 55 ; VCC = 5 V 40 Rbus 55 ; VCC = 5 V normal-power modes; -10 V VBP +15 V; -10 V VBM +15 V normal-power modes; -10 V VBP +15 V; -10 V VBM +15 V low-power modes; -10 V VBP +15 V; -10 V VBM +15 V Vi(dif)(H-L) |Vi(dif)det(act)| |Io(sc)(BP)| |Io(sc)(BM)| Ri(BP) Ri(BM) Ri(dif)(BP-BM) ILI(BP) ILI(BM) differential input voltage difference between HIGH-level and LOW-level activity detection differential input voltage (absolute value) short-circuit output current on pin BP (absolute value) short-circuit output current on pin BM (absolute value) input resistance on pin BP input resistance on pin BM differential input resistance between pin BP and pin BM input leakage current on pin BP input leakage current on pin BM normal-power modes; (VBP + VBM) / 2 = 2.5 V normal-power modes VBP = 0 V, 60 V VBM = 0 V, 60 V idle level; Rbus = idle level; Rbus = idle level; Rbus = VBP = 5 V; VBAT = VCC = VIO = 0 V VBM = 5 V; VBAT = VCC = VIO = 0 V Rbus = 45 Rbus = 45 Rbus = 45 not tested; with respect to all other pins at ground; VBP = 100 mV; f = 5 MHz not tested; with respect to all other pins at ground; VBM = 100 mV; f = 5 MHz
[1]
Min
Typ
Max
Unit
0.4VCC 0.5VCC 0.6VCC V -0.1 -7.5 -7.5 -25 600 -1500 150 0 0 800 -800 225 +0.1 +7.5 +7.5 +25 1500 -600 300 V mA mA mV mV mV mV
-60 V |VBP| +60 V -60 V |VBM| +60 V
VIL(dif)
differential LOW-level input voltage
-300
-225
-150
mV
-400
-225
-125
mV
150 10 10 10 10 20 -10 -10
225 20 20 20 20 40 0 0
10 300 35 35 40 40 80 +10 +10
% mV mA mA k k k A A
Vcm(bus)(DATA_0) DATA_0 bus common-mode voltage Vcm(bus)(DATA_1) DATA_1 bus common-mode voltage Vcm(bus) Ci(BP) bus common-mode voltage difference input capacitance on pin BP
0.4VCC 0.5VCC 0.6VCC V 0.4VCC 0.5VCC 0.6VCC V -25 0 8 +25 15 mV pF
Ci(BM)
input capacitance on pin BM
[1]
-
8
15
pF
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Preliminary data sheet
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TJA1081
FlexRay node transceiver
Table 12. Static characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. www..com Symbol Ci(dif)(BP-BM) Parameter differential input capacitance between pin BP and pin BM Conditions not tested; with respect to all other pins at ground; V(BM-BP) = 100 mV; f = 5 MHz IINH = -0.2 mA Sleep mode VINH = 0 V low-power mode VWAKE = 2.4 V for t > twake(WAKE) VWAKE = 4.6 V for t > twake(WAKE) VBAT > 5.5 V VBAT > 5.5 V
[1]
Min -
Typ 2
Max 5
Unit pF
Pin INH VOH(INH) IL(INH) IOL(INH) Pin WAKE Vth(det)(WAKE) IIL(WAKE) IIH(WAKE) detection threshold voltage on pin WAKE LOW-level input current on pin WAKE HIGH-level input current on pin WAKE 2.5 3 -11 4.5 11 -3 V A A HIGH-level output voltage on pin INH leakage current on pin INH LOW-level output current on pin INH VBAT - 0.8 -5 -15 VBAT - 0.3 0 -5 VBAT - 0.1 +5 -1 V A mA
Temperature protection Tj(warn)(medium) Tj(dis)(high) Power-on reset Vth(det)POR Vth(rec)POR Vhys(POR)
[1]
medium warning junction temperature high disable junction temperature power-on reset detection threshold voltage power-on reset recovery threshold voltage power-on reset hysteresis voltage
155 180 3.0 3.1 100
165 190 -
175 200 3.4 3.5 200
C C V V mV
These values are based on measurements taken on several samples (less than 10 pieces). These measurements have taken place in the laboratory and have been done at Tamb = 25 C and Tamb = 125 C. No characterization has been done for these parameters. No industrial test will be performed on production products.
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FlexRay node transceiver
10. Dynamic characteristics
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Table 13. Dynamic characteristics All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Pins BP and BM td(TXD-bus) delay time from TXD to bus Normal mode DATA_0 DATA_1 td(TXD-bus) td(bus-RXD) delay time difference from TXD to bus delay time from bus to RXD Normal mode; between DATA_0 and DATA_1 Normal mode; CRXD = 15 pF; see Figure 11 DATA_0 DATA_1 td(bus-RXD) delay time difference from bus to RXD Normal mode CRXD = 15 pF; between DATA_0 and DATA_1; see Figure 11 Normal mode Normal mode Normal mode Normal mode Normal mode Normal mode 10 % to 90 %; Rbus = 45 ; Cbus = 100 pF 90 % to 10 %; Rbus = 45 ; Cbus = 100 pF Standby or Sleep mode; -10 V VBP +15 V; -10 V VBM +15 V 50 50 5 ns ns ns
[1] [1]
Parameter
Conditions
Min
Typ
Max
Unit
-
-
50 50 4
ns ns ns
td(TXEN-busidle) td(TXEN-busact) td(BGE-busidle) td(BGE-busact) td(bus)(idle-act) td(bus)(act-idle) tr(dif)(bus) tf(dif)(bus)
delay time from TXEN to bus idle delay time from TXEN to bus active delay time from BGE to bus idle delay time from BGE to bus active bus delay time from idle to active bus delay time from active to idle bus differential rise time bus differential fall time
5 5
12 12
80 75 100 75 30 30 25 25
ns ns ns ns ns ns ns ns
WAKE symbol detection tdet(wake)DATA_0 tdet(wake)idle tdet(wake)tot Undervoltage tdet(uv)(VCC) trec(uv)(VCC) tdet(uv)(VIO) tdet(uv)(VBAT) tdet(act)(bus) tdet(idle)(bus) td(STBN-RXD) undervoltage detection time on pin VCC undervoltage recovery time on pin VCC undervoltage detection time on pin VIO undervoltage detection time on pin VBAT activity detection time on bus pins idle detection time on bus pins STBN to RXD delay time Vdif: 0 mV 400 mV Vdif: 400 mV 0 mV STBN HIGH to RXD HIGH; wake flag set 100 1 100 100 100 670 5.2 670 1 250 245 2 ms ms ms ms ns ns s DATA_0 wake-up detection time idle wake-up detection time total wake-up detection time 1 1 50 4 4 115 s s s
Activity detection
Mode control pins
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Preliminary data sheet
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NXP Semiconductors
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FlexRay node transceiver
Table 13. Dynamic characteristics ...continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = -40 C to +150 C; Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. www..com Symbol td(STBN-stb) th(gotosleep) Status register tdet(EN) TEN td(EN-ERRN) WAKE twake(WAKE) wake-up time on pin WAKE low-power modes; falling edge on pin WAKE; 6.5 V VBAT 27 V low-power modes; falling edge on pin WAKE; 27 V < VBAT 60 V Miscellaneous tdetCL(TXEN_BGE) TXEN_BGE clamp detection time
[1] [2] Rise and fall time (10 % to 90 %) of tr(TXD) and tf(TXD) = 5 ns 1 ns. Same parameter is guaranteed by design for the transition from Normal to Go-to-sleep mode.
Parameter
Conditions
Min 20
Typ 35 25
Max 10 50 80 20 2 100
Unit s s s s s s
delay time from STBN to standby mode STBN LOW to Standby mode; Receive-only mode[2] go-to-sleep hold time detection time on pin EN time period on pin EN delay time from EN to ERRN for mode control for reading status bits for reading status bits
20 4 5
25
75
175
s
2600
-
10400
s
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Preliminary data sheet
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
www..com Preliminary data sheet Rev. 01 -- 15 April 2009
(c) NXP B.V. 2009. All rights reserved. TJA1081_1
NXP Semiconductors
td(TXD-bus) td(TXD-bus) 0.7VIO TXD 0.3VIO td(TXEN-busidle)
td(TXEN-busact) td(BGE-busidle)
td(BGE-busact)
0.7VIO TXEN 0.3VIO
0.7VIO BGE 0.3VIO
BP and BM
+300 mV 0V -300 mV
90 % -150 mV -300 mV -150 mV -300 mV 10 %
0.7VIO RXEN 0.3VIO
0.7VIO RXD 0.3VIO td(bus-RXD) td(bus-RXD) tdet(idle)(bus) tdet(act)(bus) tdet(idle)(bus) tdet(act)(bus) tr(dif)(bus) tf(dif)(bus)
001aae445
Fig 10. Detailed timing diagram
FlexRay node transceiver
TJA1081
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Vdif (mV) 400 300
22.5 ns
22.5 ns
37.5 ns -300 -400 60 ns RXD td(bus-RXD) td(bus-RXD)
Vdif (mV) 400 300
22.5 ns
22.5 ns
37.5 ns -300 -400 60 ns RXD td(bus-RXD) td(bus-RXD)
015aaa044
Vdif is the receiver test signal.
Fig 11. Receiver test signal
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11. Test information
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+12 V +5 V
100 nF 10 F
3 VIO
16 VCC
11 VBAT BP 15
Rbus Cbus
TJA1081
BM
14
RXD
6
15 pF
015aaa070
Fig 12. Test circuit for dynamic characteristics
ISO 7637
G
12 V or 42 V
+5 V
100 nF 10 F
3 VIO
16 VCC
11 VBAT BP 15
Rbus 1 nF ISO 7637 Cbus
TJA1081
BM 14
G
1 nF
015aaa071
The waveforms of the applied transients are in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 4 and 5. Test conditions: Normal mode: bus idle Normal mode: bus active; TXD at 5 MHz and TXEN at 1 kHz Standby mode
Fig 13. Test circuit for automotive transients
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12. Package outline
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SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A X
c y HE vM A
Z 16 9
Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 14. Package outline SOT338-1 (SSOP16)
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FlexRay node transceiver
13. Soldering of SMD packages
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This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
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Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 15) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15
Table 14. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 15. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 15.
TJA1081_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 April 2009
31 of 36
NXP Semiconductors
TJA1081
FlexRay node transceiver
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 15. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 16. BSS CAN CDM ECU EMC EME EMI ESD FES HBM MM PWON TSS Abbreviations Description Byte Start Sequence Controller Area Network Charged Device Model Electronic Control Unit ElectroMagnetic Compatibility ElectroMagnetic Emission ElectroMagnetic Immunity ElectroStatic Discharge Frame End Sequence Human Body Model Machine Model Power-on Transmission Start Sequence Abbreviation
15. References
[1] [2]
TJA1081_1
EPL -- FlexRay Communications System Electrical Physical Layer Specification Version 2.1 Rev. A, FlexRay Consortium, Dec. 2005 TJA1080A -- FlexRay transceiver data sheet, www.nxp.com
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 April 2009
32 of 36
NXP Semiconductors
TJA1081
FlexRay node transceiver
16. Revision history
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Table 17. TJA1081_1
Revision history Release date 20090415 Data sheet status Preliminary data sheet Change notice Supersedes -
Document ID
TJA1081_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 April 2009
33 of 36
NXP Semiconductors
TJA1081
FlexRay node transceiver
17. Legal information
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17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications only -- This NXP Semiconductors product has been developed for use in automotive applications only. The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
17.4 Licenses
Purchase of NXP ICs with FlexRay functionality FlexRay license required. This product has been developed within the framework of the "FlexRay" consortium. FlexRay consortium members are willing to grant licenses under their essential FlexRay intellectual property rights to end users of FlexRay-enabled products upon request of an end user. The sale by NXP Semiconductors of a FlexRay-enabled product will not be construed as the granting of such a license. Each end user will have to apply to the FlexRay consortium administration to obtain such a license or to apply for membership. The FlexRay consortium can be contacted at request@flexray.com.
17.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
TJA1081_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 April 2009
34 of 36
NXP Semiconductors
TJA1081
FlexRay node transceiver
18. Contact information
www..com
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TJA1081_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 15 April 2009
35 of 36
NXP Semiconductors
TJA1081
FlexRay node transceiver
19. Contents
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1 2 2.1 2.2 2.3 2.4 2.5
3 4 5 5.1 5.2 6 6.1 6.1.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.3.1 6.3.1.1 6.3.1.2 6.3.2 6.4 6.4.1 6.4.2 6.4.3 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 6.5.9 6.5.10 6.5.11 6.5.12
General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Optimized for time triggered communication systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Low power management . . . . . . . . . . . . . . . . . 1 Diagnosis (detection and signalling) . . . . . . . . . 2 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional classes according to FlexRay electrical physical layer specification (see Ref. 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5 Bus activity and idle detection . . . . . . . . . . . . . 5 Mode control pins: STBN and EN. . . . . . . . . . . 5 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 12 Receive-only mode . . . . . . . . . . . . . . . . . . . . . 12 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 12 Go-to-sleep mode . . . . . . . . . . . . . . . . . . . . . . 12 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Wake-up mechanism . . . . . . . . . . . . . . . . . . . 13 Remote wake-up. . . . . . . . . . . . . . . . . . . . . . . 13 Bus wake-up via wake-up pattern. . . . . . . . . . 13 Bus wake-up via dedicated FlexRay data frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Local wake-up via pin WAKE . . . . . . . . . . . . . 14 Fail-silent behavior . . . . . . . . . . . . . . . . . . . . . 15 VBAT undervoltage. . . . . . . . . . . . . . . . . . . . . . 15 VCC undervoltage . . . . . . . . . . . . . . . . . . . . . . 15 VIO undervoltage. . . . . . . . . . . . . . . . . . . . . . . 15 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Local wake-up source flag . . . . . . . . . . . . . . . 15 Remote wake-up source flag . . . . . . . . . . . . . 16 Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-on flag . . . . . . . . . . . . . . . . . . . . . . . . . 16 Temperature medium flag . . . . . . . . . . . . . . . . 16 Temperature high flag . . . . . . . . . . . . . . . . . . . 16 TXEN_BGE clamped flag . . . . . . . . . . . . . . . . 16 Bus error flag . . . . . . . . . . . . . . . . . . . . . . . . . 16 UVVBAT flag . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 UVVCC flag . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 UVVIO flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.6 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19
Status register . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17 19 20 20 24 28 29 30 30 30 30 31 32 32 33 34 34 34 34 34 34 35 36
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 April 2009 Document identifier: TJA1081_1

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